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[Software Engineering] Max+Plus-II_Quickstart_Chinese DL : 0: Max+Plus II 简易用户使用入门指南
Date : 2008-10-13 Size : 229.08kb User : whr
[Books] MPII_Quickstart_Chinese DL : 0: Max+Plus II 简易用户使用入门指南-Max Plus II Summary users Beginner's Guide
Date : 2025-07-12 Size : 228kb User : 姜力
[Books] max+plus ii快速入门 DL : 0: maxplus2是一款应用于硬件编程的编程软件，本文件教你快速掌握其编程，仿真方法。-maxplus2 hardware is a programming application programming software, this document will teach you grasp its programming and simulation methods.
Date : 2025-07-12 Size : 336kb User : 刘晓飞
[Other] wave0001 DL : 0: 在MAX-PLUS下设计的函数消耗发生器，波形有正弦波、方波、三角拨、锯齿波（用键盘选择），信号频率可调（用键盘调节）-the MAX-PLUS design of the consumption function generator, a sine wave, square, triangle area and Sawtooth (keyboard), in signal frequency adjustable (keyboard conditioning)
Date : 2025-07-12 Size : 130kb User : 曹海学
[Other] VHDL-FPGA-clock DL : 1: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Date : 2025-07-12 Size : 263kb User : 王越
[VHDL-FPGA-Verilog] shuzizhong05 DL : 0: MAX+plus II 9.23 Baseline-MAX plus Baseline II 9.23
Date : 2025-07-12 Size : 252kb User : 冬海
[VHDL-FPGA-Verilog] DigitalClockVHDL DL : 0: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Date : 2025-07-12 Size : 82kb User : wangyiran
[File Format] MAX+PLUSII DL : 0: MAX+PLUSII不错的电子书,内容详细,易懂.-MAX PLUSII good e-books, detailed, understandable.
Date : 2025-07-12 Size : 256kb User : zhoudefang
[Program doc] MAX+plusIIxiaVHDLsheji DL : 0: VHDL在MAX+plusII下进行的电路设计!是一个WORD文档!-VHDL in MAX+ PlusII carried out under the circuit design! Is a WORD document!
Date : 2025-07-12 Size : 12kb User : 段正伟
[Other] 1_061227123744 DL : 0: max plus的入门与应用，适合初学者对max plus ii有一个感性的认识-max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of
Date : 2025-07-12 Size : 232kb User : da
[Other] MAX+PLUS DL : 0: 看看一步一步学听好的挺简单的适合出学的看一步一步学听好的挺简单的适合出学的-To see step by step, learn to listen to good for a very simple step by step to learn to see learn to listen to very good for a simple learning
Date : 2025-07-12 Size : 437kb User :
[VHDL-FPGA-Verilog] taxi-vhdl DL : 0: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Date : 2025-07-12 Size : 47kb User : aneeee
[VHDL-FPGA-Verilog] electoniclock DL : 0: 摘　要: 数字密码锁主要完成上锁、密码输入、密码核对、开启电锁、密码修改等功能.数字密码锁的设计电路主要包括 11 个模块 ,各模块由相应的 VHDL 程序具体实现并分别进行了 MAX + PLUS II 时序仿真. 最后 ,在 MAX + PLUS Ⅱ环境下进行了整体电路的模拟仿真 ,结果表明 ,整个设计满足要求.
Date : 2025-07-12 Size : 696kb User : 孙光华
[Software Engineering] Max+Plus-II_Quickstart_Chinese DL : 0: Max+Plus II 简易用户使用入门指南-Max+ Plus II Simple User Getting Started Guide
Date : 2025-07-12 Size : 229kb User : whr
[VHDL-FPGA-Verilog] 0097 DL : 0: MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!
Date : 2025-07-12 Size : 13kb User : LEE
[VHDL-FPGA-Verilog] MAX-PLUSII-soft DL : 0: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Date : 2025-07-12 Size : 122kb User : 徐靖
[Software Engineering] 07302529 DL : 0: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Date : 2025-07-12 Size : 239kb User : 翁浩达
[VHDL-FPGA-Verilog] Max_PlusII_ppt DL : 0: Max+Plus II 的ppt文档，看后可以很轻易上手Max+Plus -Help
Date : 2025-07-12 Size : 1.62mb User : 李晓东
[VHDL-FPGA-Verilog] WATERHOURMETERBASEDONVHDL DL : 0: 在 MAX+PLUS II开发环境下采用 VHDL语言设计并实现了电表抄表器讨论了系统的四个组成模块的设计和 VHDL 的实现每个模块采用 RTL 级描述整体的生成采用图形输入法通过波形仿真下载芯片测试完成了抄表器的功能-In the MAX+ PLUS II development environment using VHDL language design and implementation of the meter meter reading device to discuss the four components of the system module design and VHDL implementation of each module using RTL-level description of a whole generation of graphical input waveform Simulation download chip testing completed meter reading functions
Date : 2025-07-12 Size : 234kb User : linfeng
[VHDL-FPGA-Verilog] fir-filter-design-using-fpga-with-MAX-Plus2 DL : 1: 基于FPGA的高阶FIR滤波器设计用max-plus　－II软件仿真-fir filter using fpga with max-plusII
Date : 2025-07-12 Size : 2.23mb User : 星空心晴之夏

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